1. Field of the Invention
The present invention relates to a complementary-type clock generator, and in particular-to an improved complementary-type clock generator which generates a normal clock signal and an inverted clock signal with minimal time differences.
2. Description of the Conventional Art
FIG. 1 shows a conventional complementary-type clock generator, which includes an inverting unit 1 for inverting an external clock signal CLKin, a buffer 2 for inverting the external clock signal CLKin, and inverters I2 and I5 for inverting the output of the inverting unit 1 and the buffer 2 and for outputting a normal clock signal CLKout and an inverted clock signal CLKoutB.
The operation of the conventional complementary-type clock generator will now be explained with reference to FIG. 1.
To begin with, when an externally applied clock signal CLKin is inputted to the inverting unit 1 and the buffer 2, respectively, the inverter I1 inverts the clock signal CLKin and outputs an inverted clock signal, and the inverters I3 and I4 sequentially invert the inputted clock signal CLKin and outputs a normal clock signal.
Thereafter, the inverter I2 re-inverts inverted clock signal outputted from the inverting unit 1 and outputs a normal clock signal CLKout, and the inverter I5 re-inverts the normal clock signal outputted from the buffer 2 and outputs an inverted clock signal CLKoutB.
However, since the conventional complementary-type has an asymmetrical construction between the inverting unit having an odd number of inverters and the buffer having an even number of inverters, there exists a prescribed time difference between a normal clock signal and an inverted clock signal.
Therefore, in order to compensate the time difference therebetween, it is necessary to accurately adjust the driving capacitance of each element. In addition, the adjusted capacitance may easily be varied due to various factors such as fabrication error, temperature, voltage or the like.